Posts | Anuj Pathania

Hosted Dr. Mitra Nasri for an invited talk 'Past, Present, and Future Trends in Real-Time Systems Research'.

Wed, 06 Sep 2023 00:00:00 +0000

Abstract: Real-time systems are pervasive in the automotive, robotics, smart industry, manufacturing, and healthcare domains, where the system’s safety, dependability, or quality of service depends on both functional and temporal correctness, namely, performing the right actions at the right time. Guaranteeing temporal correctness often involves bounding the worst-case end-to-end response-time of the system (e.g., from the moment input data are sent by a sensor to the moment the system responds to it). Bounding the response-time, in turn, requires detailed knowledge about how the underlying hardware platform, operating system, and software components/applications interact with each other and how that interaction influences the timing behavior of the system. This talk presents the past, current, and future trends in modeling, designing, and verifying real-time systems. It walks through the challenges that new hardware, software, and network technologies introduce in the verification of temporal correctness and discusses existing solutions and open research problems.

Short Bio: Mitra Nasri is an Assistant Professor at the IRIS group in the Mathematics and Computer Science Department of the Eindhoven University of Technology (TU/e). She received her PhD from the University of Tehran, in 2015. Before joining TU/e, she was an assistant professor at Delft University of Technology (TUDelft), a postdoc fellow at the Max Planck Institute for Software Systems (MPI-SWS), Germany, and a postdoc researcher at TU-Kaiserslautern, Germany. Her research interests include modeling, designing, and verifying real-time systems. She has contributed to several outstanding scheduling policies for embedded real-time systems and a formal verification framework for timing analysis and assessment of temporal correctness of multicore real-time systems. To date, she has published more than 50 papers on those topics in peer-reviewed conferences and journals. Her research has been recognized by the Best-Paper Award of RTAS’22 and RTNS’16, and the Outstanding-Paper Award of RTSS’20 and RTAS’17. Since 2022, she has been an executive member of the IEEE Technical Committee on Real-Time Systems (TCRTS) which steers RTSS, RTAS and ICCPS conferences, and the IEEE Benelux chapter on Communication and Vehicular Technology (COM/VT). She has received a Delft Technology Fellowship Award (2018), an Alexander von Humboldt Fellowship Award for post-doctoral researchers (2016), and a German Academic Exchange Service (DAAD) scholarship for young researchers (2013).

Joris op ten Berg successfully defended his Master thesis (with Cum Laude) entitled 'QoS-Aware CPU Scheduling on Simulated Multi-Core Hardware'. Congratulations, Joris!

Mon, 28 Aug 2023 00:00:00 +0000

Abstract: 3D-stacking is a new approach to building CPUs that has the potential to increase performance thanks to low memory access latency. However, stacking components on top of each other increases power density, which results in worse thermals. Higher temperatures in turn cause chips to degrade faster and become less reliable. Schedulers that make decisions to preserve reliability are one of the ways to deal with this challenge. Existing solutions tend to rely on design-time decisions or only use temperature data. We have extended CoMeT, a simulation toolchain capable of simulating 3D-stacked chips, such that it can be used to develop reliability-aware schedulers. To achieve this, we implemented a reliability model that takes temperature and supply voltage into account, and produces a metric of reliability over time. We found that this metric can be used to make scheduling decisions that are aware of a core’s history. Furthermore, we found that using data from the components inside a core could make for more accurate schedulers than when data is collected on the core as a whole.

Jurre Wolff successfully defended his Master thesis (with Cum Laude) entitled 'QoS-Aware CPU Scheduling on Simulated Multi-Core Hardware'. Congratulations, Jurre!

Mon, 28 Aug 2023 00:00:00 +0000

Abstract: This thesis introduces program-specific performance statistics as a Central Processing Unit (CPU) scheduling parameter within the context of the HotSniper chip architecture simulation toolchain. The parameter allows for a higher level of program-tailored scheduling, as opposed to the ubiquitous metrics such as types of latency and CPU utilization. The chip architecture simulator context allows for the development of novel scheduling policies for hard-to-obtain or future CPU architectures. The implementation of the parameter is guided through the first research question concerning how the HotSniper toolchain can be expanded with the Heartbeat framework, which in turn allows for the measurement of program performance. With this question answered, the performance data of eight PARSEC benchmark suite programs is collected and analyzed in pursuit to answer the second research question. This question aims to identify the natural heartbeat profiles and their relation to performance for each of these programs. The third research question then aims to answer whether program performance data can increase task scheduling effectiveness over existing metrics. To help answer these research questions, the HotSniper toolchain is used as a foundation in the form of a practical case study. HotSniper is expanded with functionality allowing for the collection of performance data which is visualized into graphs, revealing program performance profiles.

The collected data of the x264 program resulted in the implementation of a new Quality of Service (QoS) aware Dynamic Voltage and Frequency Scaling (DVFS) policy. It is found that the programspecific performance data allows for setting and achieving QoS targets. For x264, a target of 30 Frames per Second (FPS) is achieved resulting in reduced frequency and power consumption. Based on the results, this study provides five contributions to the computer architecture simulation- and scheduling algorithm research communities. First, a set of eight PARSEC benchmark programs, amended with the Heartbeat framework are provided, along with documentation on how programs in general can be supported. Second, the performance profiles of these programs are collected and analyzed, providing a greater understanding of their runtime behavior and potentially inspiring future research. Third, tooling that supports researchers with post-simulation heartbeat data analysis. Fourth, the HotSniper scheduling Application Programming Interface (API) is updated, allowing for real-time use of performance data and thus the development of performance-aware scheduling policies. Fifth, several identified research directions for future work.

The paper 'Lifetime Estimation for Core-Failure Resilient Multi-Core Processors' was accepted for IEEE MCSoC '23

Thu, 10 Aug 2023 00:00:00 +0000

Abstract: Multi-core processors come with several cores integrated on a single die. They often work incessantly under high thermal stress, leading to severe wear-out. Server-class multicores already come with a mechanism to survive a core failure called Core Failure Resilience (CFR). Embedded multi-cores with CFR are already on the horizon. The surviving cores must take on an additional workload from their fellow failed core(s) under CFR. They must also operate on higher frequencies to continue meeting the target performance. However, this additional workload assignment further accelerates the wear-out of the surviving cores due to additional heat from higher frequency operation. Lifetime estimation frameworks rely on detailed simulations, which leads to long simulation times. These frameworks are unsuitable for the early stages of the design process as they cannot quickly evaluate many design points. Existing frameworks cannot estimate the Mean Time to Failure (MTTF) for multicores that include Core-Failure Resilient (CFR) capabilities. We introduce SLICER, the first framework for estimating the MTTF of CFR multi-cores. SLICER integrates with state-of-the-art tools HotSniper and MatEx for fast and accurate MTTF estimation.

The demo/tool 'ARM-CO-UP: ARM Co-Operative Utilization of Processors' was accepted for the Embedded Systems Software Competition at the IEEE/ACM Embedded Systems Week 2023.

Tue, 01 Aug 2023 00:00:00 +0000

Abstract: Heterogeneous Multi-Processor System on Chips (HMPSoCs) combines different processors on a single chip. They enable powerful embedded devices, which increasingly perform Machine Learning (ML) inference at the edge. State-of-the-art HMPSoCs can perform on-chip embedded inference using their CPU, GPU, and integrated accelerators. The on-chip GPU in embedded devices is comparable in performance to CPU clusters, and efficient inference requires the cooperative utilization of these processors. Integrated accelerators, although operating with lower bit precision, significantly improve power efficiency at the expense of model accuracy.

However, existing inference frameworks for edge devices typically utilize only a single processor type and lack the ability to use different processor types collaboratively. To this end,We design the ARM-COUP framework based on the ARM-CL framework. The ARM-COUP provides both parallel and serial utilization of different processor types. In parallel mode, it optimizes throughput(FPS) and energy efficiency by leveraging pipeline execution of network partitions for consecutive input data. While in serial mode, it improves inference latency and energy efficiency through layer-switch inference for each input data and layer-wise DVFS. It automates model graph partitioning and mapping, pipeline synchronization, processor type switching, layer-wise DVFS, and integration of new accelerators, even with closed-source libraries.

The paper 'PELSI: Power-Efficient Layer-Switched Inference' has been nominated for the Best Paper Award at IEEE RTCSA '23!

Thu, 06 Jul 2023 00:00:00 +0000

Abstract: Convolutional Neural Networks (CNNs) are now quintessential kernels within embedded computer vision applications deployed in edge devices. Heterogeneous Multi-Processor Systemon- Chips (HMPSoCs) with Dynamic Voltage and Frequency Scaling (DVFS) capable components (CPUs and GPUs) allow for lowlatency, low-power CNN inference on resource-constrained edge devices when employed efficiently.

CNNs comprise several heterogeneous layer types that execute with different degrees of power efficiency on different HMPSoC components at different frequencies.We propose the first framework, PELSI, that exploits this layer-wise power efficiency heterogeneity for power-efficient CPU-GPU layer-switched CNN interference on HMPSoCs. PELSI executes each layer of a CNN on an HMPSoC component (CPU or GPU) clocked at just the right frequency for every layer such that the CNN meets its inference latency target with minimal power consumption while still accounting for the powerperformance overhead of multiple switching between CPU and GPU mid-inference. PELSI incorporates a Genetic Algorithm (GA) to identify the near-optimal CPU-GPU layer-switched CNN inference configuration from within the large exponential design space that meets the given latency requirement most power efficiently.

We evaluate PELSI on Rock-Pi embedded platform. The platform contains an RK3399Pro HMPSoC with DVFS-capable CPU clusters and GPU. Empirical evaluations with five different CNNs show a 44.48% improvement in power efficiency for CNN inference under PELSI over the state-of-the-art.

Erik Leonards successfully defended his Bachelor thesis (with Cum Laude) entitled 'Processor Modelling Using Queueing Theory'. Congratulations, Erik!

Mon, 03 Jul 2023 00:00:00 +0000

Abstract: This thesis gives a general introduction into closed queueing networks, describes mean value analysis and formulates a closed queueing network model that predicts the parallel execution time of multiple benchmarks when the isolated execution time is known. The model aims at imitating the main source of interference between the benchmarks: the DRAM. For an n-core processor, the model comprises n + 1 queues: n cores and the DRAM.

The isolated execution of a benchmark is used to determine the model parameters. The model parameters are chosen such that the measured DRAM throughput and access latency correspond to the DRAM throughput and access latency of the model. The real DRAM throughput and access latency of a benchmark are obtained with the simulation software CoMeT [7], while the DRAM throughput and access latency from the model are obtained from mean value analysis [6].

The accuracy of the model is determined by comparing the parallel benchmark execution time of the model to the real parallel benchmark execution time. This is done for 6 benchmarks in the PARSEC [3] benchmarks suite. For 2 of the benchmarks, the model could very accurately predict the parallel execution time, while the model was less accurate for the other 4 benchmarks.

I will be serving in the Technical Program Committee for SAMOS 2023.

Sun, 02 Jul 2023 00:00:00 +0000

The paper 'Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power Regulation' was accepted for publication at IEEE/ACM CODES+ISSS'23.

Sat, 01 Jul 2023 00:00:00 +0000

The paper 'PELSI: Power-Efficient Layer-Switched Inference' was accepted for publication at IEEE RTCSA '23.

Tue, 30 May 2023 00:00:00 +0000

The paper '3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems' was accepted for publication at IEEE ISVLSI '23.

Thu, 04 May 2023 00:00:00 +0000

Featured in UvA news article title 'Theme-Based Collaboration Enters Next Phase With Awarding of Midsize Projects and Seed Grants'.

Wed, 03 May 2023 00:00:00 +0000

Participated as panelist on topic 'The rise of AI applications like ChatGPT and their impact on Cybersecurity' at Dycpher Donerdag.

Tue, 02 May 2023 00:00:00 +0000

I will be serving in the Technical Program Committee for DATE 2023.

Mon, 17 Apr 2023 00:00:00 +0000

IP Thema project 'Energy Labels for Ecologically Sustainable Digital Services - A Technological, Behavioural, and Legal Perspective' granted!

Fri, 14 Apr 2023 00:00:00 +0000

The patent 'Power management for multicore processors' has been successfully published under number EP 4 152 124.

Wed, 05 Apr 2023 00:00:00 +0000

I will be serving in the Technical Program Committee for ASP-DAC 2023.

Mon, 16 Jan 2023 00:00:00 +0000

I will be serving in the Technical Program Committee for VLSID 2023.

Fri, 06 Jan 2023 00:00:00 +0000

The paper 'HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction' was accepted for DATE 2021.

Tue, 15 Nov 2022 00:00:00 +0000

The paper 'Thermal Management for S-NUCA Many-Cores via Synchronous Thread Rotations' was accepted at DATE 2023.

Tue, 15 Nov 2022 00:00:00 +0000

Featured in UvA news article title 'In the Future We Will Have Energy Labels for Our Digital Services'.

Thu, 03 Nov 2022 00:00:00 +0000

I will be serving in the Technical Program Committee for SLIP 2022.

Wed, 02 Nov 2022 00:00:00 +0000

I will be serving in the Technical Program Committee for ICCAD 2022.

Sat, 29 Oct 2022 00:00:00 +0000

I will be serving in the Technical Program Committee for HiPC 2022.

Tue, 18 Oct 2022 00:00:00 +0000

I will be serving in the Organizing Committee for ESWeek 2022 as Media Chair.

Sat, 08 Oct 2022 00:00:00 +0000

I will be serving in the Technical Program Committee for CASES 2022.

Sat, 08 Oct 2022 00:00:00 +0000

I will be serving in the Technical Program Committee for MLCAD 2022.

Sun, 11 Sep 2022 00:00:00 +0000

I will be serving in the Technical Program Committee for DSD 2022.

Tue, 06 Sep 2022 00:00:00 +0000

Leo Schreuders successfully defended his Master thesis (with Cum Laude) entitled 'Combined Core-Memory Dynamic Thermal Management in 3D Core-Memory Architectures'. Congratulations, Leo!

Sun, 28 Aug 2022 00:00:00 +0000

The chapter 'Pipelined CNN Inference on Heterogeneous Multi-Processor System-on-Chip' was accepted for the book on Embedded Machine Learning for Cyber Physical, IoT, and Edge Computing (Springer).

Mon, 08 Aug 2022 00:00:00 +0000

Martijn Besamusca successfully defended his Bachelor thesis entitled 'The Thermal And Performance Impact Of 3D Stacking L3 Caches In Processors'. Congratulations, Martijn!

Tue, 19 Jul 2022 00:00:00 +0000

Given an invited talk 'Getting Started with Interval Thermal Simulations' at TU Wien

Thu, 14 Jul 2022 00:00:00 +0000

I will be serving in the Organizing Committee for SAMOS 2022 as Publicity Chair.

Sat, 02 Jul 2022 00:00:00 +0000

I will be serving in the Technical Program Committee for SAMOS 2022.

Sat, 02 Jul 2022 00:00:00 +0000

The paper 'CPU-GPU Layer-Switched Low Latency CNN Inference' was accepted for Euromicro DSD 2022.

Fri, 17 Jun 2022 00:00:00 +0000

The paper 'CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5 D, and 3D Processor-Memory System' was accepted for ACM Transactions on Architecture and Code (TACO).

Thu, 14 Apr 2022 00:00:00 +0000

I will be serving in the Technical Program Committee for VLSID 2022.

Thu, 06 Jan 2022 00:00:00 +0000

Featured in UvA news article title 'Boosting Processor Performance by Optimizing the Use of its Temperature'.

Thu, 09 Dec 2021 00:00:00 +0000

The paper 'HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction' was accepted for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Mon, 08 Nov 2021 00:00:00 +0000

I will be serving in the Technical Program Committee for ICCAD 2021.

Fri, 29 Oct 2021 00:00:00 +0000

I will be serving in the Technical Program Committee for ICCAD 2023.

Fri, 29 Oct 2021 00:00:00 +0000

I will be serving in the Technical Program Committee for HiPC 2021.

Mon, 18 Oct 2021 00:00:00 +0000

I will be serving in the Organizing Committee for ESWeek 2021 as Web Chair.

Fri, 08 Oct 2021 00:00:00 +0000

I will be serving in the Technical Program Committee for CASES 2021.

Fri, 08 Oct 2021 00:00:00 +0000

The paper 'T-TSP: Transient-Temperature Based Safe Power Budgeting in Multi-/Many-Core Processors' was accepted for IEEE ICCD 2021.

Fri, 17 Sep 2021 00:00:00 +0000

I will be serving in the Technical Program Committee for MLCAD 2021.

Sat, 11 Sep 2021 00:00:00 +0000

Science & Design project 'Towards Zero-Waste Computing: Energy Labels for Digital Services' granted!

Tue, 24 Aug 2021 00:00:00 +0000

I will be serving in the Technical Program Committee for DAC 2021.

Fri, 09 Jul 2021 00:00:00 +0000

I will co-chairing a session in DAC 2021.

Fri, 09 Jul 2021 00:00:00 +0000

I will be serving in the Organizing Committee for SAMOS 2021 as Submission Chair.

Fri, 02 Jul 2021 00:00:00 +0000

I will be serving in the Technical Program Committee for SAMOS 2021.

Fri, 02 Jul 2021 00:00:00 +0000

The paper 'ChordMap: Automated Mapping of Streaming Applications onto CGRA' was accepted for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Sun, 17 Jan 2021 00:00:00 +0000

I will be serving in the Technical Program Committee for VLSID 2021.

Wed, 06 Jan 2021 00:00:00 +0000

I will be serving in the Technical Program Committee for ICCD 2020.

Tue, 17 Nov 2020 00:00:00 +0000

I will be serving in the Technical Program Committee for CASES 2020.

Thu, 08 Oct 2020 00:00:00 +0000

I will be serving in the Technical Program Committee for MLCAD 2020.

Fri, 11 Sep 2020 00:00:00 +0000

I will be serving in the Technical Program Committee for DAC 2020.

Thu, 09 Jul 2020 00:00:00 +0000

I will co-chairing a session in DAC 2020.

Thu, 09 Jul 2020 00:00:00 +0000

I will be serving in the Technical Program Committee for SAMOS 2020.

Thu, 02 Jul 2020 00:00:00 +0000

I will be serving in the Technical Program Committee for VLSID 2020.

Mon, 06 Jan 2020 00:00:00 +0000

I will co-chair a session VLSID 2020.

Mon, 06 Jan 2020 00:00:00 +0000

I will be serving in the Technical Program Committee for ICCD 2019.

Sun, 17 Nov 2019 00:00:00 +0000

I will be serving in the Technical Program Committee for CASES 2019.

Tue, 08 Oct 2019 00:00:00 +0000

I will be serving in the Technical Program Committee for SAMOS 2019.

Tue, 02 Jul 2019 00:00:00 +0000

I will be serving in the Technical Program Committee for RTSS 2019.

Wed, 01 May 2019 00:00:00 +0000

The paper 'QoS-Aware Stochastic Power Budgeting for Many-Cores' recieved HiPEAC 2018 Paper Award.

Fri, 01 Jun 2018 00:00:00 +0000

The paper 'Scalable Probabilistic Power Budgeting for Many-Cores' has been nominated for the Best Paper Award at Design Automation and Test in Europe '17!

Fri, 01 Sep 2017 00:00:00 +0000

The paper 'Distributed Scheduling for Many-Cores Using Cooperative Game Theory' recieved HiPEAC 2016 Paper Award.

Wed, 01 Jun 2016 00:00:00 +0000