Anuj Pathania
Anuj Pathania
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The paper '3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems' was accepted for publication at IEEE ISVLSI '23.
May 4, 2023
Featured in UvA news article title 'Theme-Based Collaboration Enters Next Phase With Awarding of Midsize Projects and Seed Grants'.
May 3, 2023
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Participated as panelist on topic 'The rise of AI applications like ChatGPT and their impact on Cybersecurity' at Dycpher Donerdag.
May 2, 2023
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I will be serving in the Technical Program Committee for DATE 2023.
Apr 17, 2023
IP Thema project 'Energy Labels for Ecologically Sustainable Digital Services - A Technological, Behavioural, and Legal Perspective' granted!
Apr 14, 2023
The patent 'Power management for multicore processors' has been successfully published under number EP 4 152 124.
Apr 5, 2023
I will be serving in the Technical Program Committee for ASP-DAC 2023.
Jan 16, 2023
I will be serving in the Technical Program Committee for VLSID 2023.
Jan 6, 2023
The paper 'HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction' was accepted for DATE 2021.
Nov 15, 2022
The paper 'Thermal Management for S-NUCA Many-Cores via Synchronous Thread Rotations' was accepted at DATE 2023.
Nov 15, 2022
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