Anuj Pathania
Anuj Pathania
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Martijn Besamusca successfully defended his Bachelor thesis entitled 'The Thermal And Performance Impact Of 3D Stacking L3 Caches In Processors'. Congratulations, Martijn!
Jul 19, 2022
Given an invited talk 'Getting Started with Interval Thermal Simulations' at TU Wien
Jul 14, 2022
I will be serving in the Organizing Committee for SAMOS 2022 as Publicity Chair.
Jul 2, 2022
I will be serving in the Technical Program Committee for SAMOS 2022.
Jul 2, 2022
The paper 'CPU-GPU Layer-Switched Low Latency CNN Inference' was accepted for Euromicro DSD 2022.
Jun 17, 2022
The paper 'CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5 D, and 3D Processor-Memory System' was accepted for ACM Transactions on Architecture and Code (TACO).
Apr 14, 2022
I will be serving in the Technical Program Committee for VLSID 2022.
Jan 6, 2022
Featured in UvA news article title 'Boosting Processor Performance by Optimizing the Use of its Temperature'.
Dec 9, 2021
Article Link
The paper 'HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction' was accepted for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
Nov 8, 2021
I will be serving in the Technical Program Committee for ICCAD 2021.
Oct 29, 2021
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