Student | Anuj Pathania

Joris op ten Berg successfully defended his Master thesis (with Cum Laude) entitled 'QoS-Aware CPU Scheduling on Simulated Multi-Core Hardware'. Congratulations, Joris!

Mon, 28 Aug 2023 00:00:00 +0000

Abstract: 3D-stacking is a new approach to building CPUs that has the potential to increase performance thanks to low memory access latency. However, stacking components on top of each other increases power density, which results in worse thermals. Higher temperatures in turn cause chips to degrade faster and become less reliable. Schedulers that make decisions to preserve reliability are one of the ways to deal with this challenge. Existing solutions tend to rely on design-time decisions or only use temperature data. We have extended CoMeT, a simulation toolchain capable of simulating 3D-stacked chips, such that it can be used to develop reliability-aware schedulers. To achieve this, we implemented a reliability model that takes temperature and supply voltage into account, and produces a metric of reliability over time. We found that this metric can be used to make scheduling decisions that are aware of a core’s history. Furthermore, we found that using data from the components inside a core could make for more accurate schedulers than when data is collected on the core as a whole.

Jurre Wolff successfully defended his Master thesis (with Cum Laude) entitled 'QoS-Aware CPU Scheduling on Simulated Multi-Core Hardware'. Congratulations, Jurre!

Mon, 28 Aug 2023 00:00:00 +0000

Abstract: This thesis introduces program-specific performance statistics as a Central Processing Unit (CPU) scheduling parameter within the context of the HotSniper chip architecture simulation toolchain. The parameter allows for a higher level of program-tailored scheduling, as opposed to the ubiquitous metrics such as types of latency and CPU utilization. The chip architecture simulator context allows for the development of novel scheduling policies for hard-to-obtain or future CPU architectures. The implementation of the parameter is guided through the first research question concerning how the HotSniper toolchain can be expanded with the Heartbeat framework, which in turn allows for the measurement of program performance. With this question answered, the performance data of eight PARSEC benchmark suite programs is collected and analyzed in pursuit to answer the second research question. This question aims to identify the natural heartbeat profiles and their relation to performance for each of these programs. The third research question then aims to answer whether program performance data can increase task scheduling effectiveness over existing metrics. To help answer these research questions, the HotSniper toolchain is used as a foundation in the form of a practical case study. HotSniper is expanded with functionality allowing for the collection of performance data which is visualized into graphs, revealing program performance profiles.

The collected data of the x264 program resulted in the implementation of a new Quality of Service (QoS) aware Dynamic Voltage and Frequency Scaling (DVFS) policy. It is found that the programspecific performance data allows for setting and achieving QoS targets. For x264, a target of 30 Frames per Second (FPS) is achieved resulting in reduced frequency and power consumption. Based on the results, this study provides five contributions to the computer architecture simulation- and scheduling algorithm research communities. First, a set of eight PARSEC benchmark programs, amended with the Heartbeat framework are provided, along with documentation on how programs in general can be supported. Second, the performance profiles of these programs are collected and analyzed, providing a greater understanding of their runtime behavior and potentially inspiring future research. Third, tooling that supports researchers with post-simulation heartbeat data analysis. Fourth, the HotSniper scheduling Application Programming Interface (API) is updated, allowing for real-time use of performance data and thus the development of performance-aware scheduling policies. Fifth, several identified research directions for future work.

Erik Leonards successfully defended his Bachelor thesis (with Cum Laude) entitled 'Processor Modelling Using Queueing Theory'. Congratulations, Erik!

Mon, 03 Jul 2023 00:00:00 +0000

Abstract: This thesis gives a general introduction into closed queueing networks, describes mean value analysis and formulates a closed queueing network model that predicts the parallel execution time of multiple benchmarks when the isolated execution time is known. The model aims at imitating the main source of interference between the benchmarks: the DRAM. For an n-core processor, the model comprises n + 1 queues: n cores and the DRAM.

The isolated execution of a benchmark is used to determine the model parameters. The model parameters are chosen such that the measured DRAM throughput and access latency correspond to the DRAM throughput and access latency of the model. The real DRAM throughput and access latency of a benchmark are obtained with the simulation software CoMeT [7], while the DRAM throughput and access latency from the model are obtained from mean value analysis [6].

The accuracy of the model is determined by comparing the parallel benchmark execution time of the model to the real parallel benchmark execution time. This is done for 6 benchmarks in the PARSEC [3] benchmarks suite. For 2 of the benchmarks, the model could very accurately predict the parallel execution time, while the model was less accurate for the other 4 benchmarks.

Leo Schreuders successfully defended his Master thesis (with Cum Laude) entitled 'Combined Core-Memory Dynamic Thermal Management in 3D Core-Memory Architectures'. Congratulations, Leo!

Sun, 28 Aug 2022 00:00:00 +0000

Martijn Besamusca successfully defended his Bachelor thesis entitled 'The Thermal And Performance Impact Of 3D Stacking L3 Caches In Processors'. Congratulations, Martijn!

Tue, 19 Jul 2022 00:00:00 +0000