0010C |
(ANNCTRL2)
|
Annunciator control
[AON XTRA LA6 LA5]
(on extra io busy)
|
0010B |
ANNCTRL
|
Annunciator control
[LA4 LA3 LA2 LA1]
(alarm alpha -> <-)
|
00101 |
(CONTRAST)
|
5 bit value for contrast.
[CON3 CON2 CON1 CON0]
|
00104 |
CRC
|
4 nibbles for CRC.
Every memory fetch updates CRC.
|
00120 |
(DISPADDR)
|
Display start address
write-only
|
00100 |
(DISPIO)
|
Display bit offset for
scrolling and DON (display on)
|
00102 |
(DISPTEST)
|
High bit of contrast and
display test bits.
|
00125 |
(LINEOFFS)
|
3 nibble offset for display
write-only
|
00128 |
(LINECOUNT)
|
Display line counter
[LC3 LC2 LC1 LC0]
and miscellaneous
[DA19 M32 LC5 LC4]
|
00130 |
(MENUADDR)
|
Menu display start addr
write-only
|
00108 |
(POWERSTATUS)
|
Low power registers
|
00109 |
(POWERCTRL)
|
Low power detection
|
00137 |
TIMER1
|
1 nibble timer
decremented 16 times/s
|
00138 |
TIMER2
|
8 nibble timer
decremented 8192 times/s
|
0012E |
(TIMER1CTRL)
|
TIMER1 control
[SRQ WKE INT XTRA]
|
0012F |
(TIMER2CTRL)
|
TIMER2 control
[SRQ WKE INT TRUN]
|