**Diagrams for assignment 1**
*****************************************************************************************
* *
* Clock *
* +-------------+ *
* | | *
* | | *
* +------*------+ *
* | *
* | *
* CPU | Memory *
* +-----------------+ | +-----------------+ *
* | CLK *<---------+------------->* CLK | *
* | | | | *
* | MemDone *<------------------------* Done | *
* | | | | *
* | MemFunc *------------------------>* Func | *
* | | | | *
* | MemAddr *------------------------>* Addr | *
* | | | | *
* | MemData *<----------------------->* Data | *
* +-----------------+ +-----------------+ *
* *
*****************************************************************************************
[Figure [model]: The cpu-memory model given in assignment 1]
*****************************************************************************************
* *
* CPU MEM *
* | func, addr, data | waiting for func change *
* START WRITE |---------------------------------->| func changed *
* +-| | read func, addr and data *
* | | |-+ *
* 1 cycle --+ | | | *
* | | write "ZZZZZ..ZZ" on data | | *
* +-|---------------------------------->| | *
* | (to release channel) | | *
* | | | *
* | | +-- 99 cycles *
* wait for done | | | *
* | | | *
* | | | *
* | done | | *
* done received |<----------------------------------|-+ *
* +-| | *
* | | | wait func changed *
* 1 cycle --+ | | *
* | | | *
* +-| | *
* write finished| | *
* | | *
* | func, addr | *
* START READ |---------------------------------->|-+ func changed *
* | | | *
* | | | *
* | | | *
* | | | *
* | | | *
* wait for done | | +-- 99 cycles *
* | | | *
* | | | *
* | | | *
* | data, done | | *
* done received |<----------------------------------|-+ *
* read data | | *
* +-| |-+ *
* | | | | *
* | | | | *
* 1 cycle --+ | | +-- 1 cycle *
* | | write "ZZZZZ..ZZ" on data | | *
* +-|<----------------------------------|-+ *
* read finished| (to release channel) | *
* NEXT R/W.. | | *
* | | *
* v v *
* *
*****************************************************************************************
[Figure [module-interaction]: Shows the signaling between the CPU and Memory component. The CPU does a write followed by a read.]