Anuj Pathania

Anuj Pathania

Assistant Professor

University of Amsterdam

Biography

Anuj Pathania is an Assistant Professor in the Parallel Computing Systems (PCS) group at the University of Amsterdam (UvA). His research focuses on the design of sustainable systems deployed in power-, thermal-, energy- and reliability-constrained environments.

Interests
  • Low Power Design
  • Sustainable Systems
  • Electronic Design Automation
Education

  • PhD in Computer Science, 2018

    Karlsruhe Institute of Technology

  • MSc in Computer Science, 2012

    National University of Singapore

  • B.Tech. in Computer Science, 2009

    Maharaja Agrasen Institute of Technology

Publications

Yixian Shen, Leo Schreuders, Anuj Pathania, Andy Pimentel (2023). Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power Regulation. ACM Transactions on Embedded Computing Systems.

Ehsan Aghapour, Dolly Sapra, Andy Pimentel, Anuj Pathania (2023). PELSI: Power-Efficient Layer-Switched Inference. International Conference on Embedded and Real-Time Computing Systems and Applications.

Best Paper Award Nomination

Sobhan Niknam, Yixian Shen, Anuj Pathania, Andy Pimentel (2023). 3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems. IEEE Computer Society Annual Symposium on VLSI.

Yixian Shen, Sobhan Niknam, Anuj Pathania, Andy Pimentel (2023). Thermal Management for S-NUCA Many-Cores via Synchronous Thread Rotations. Design Automation and Test in Europe.

PDF Cite Code DOI

Sobhan Niknam, Anuj Pathania, Andy Pimentel (2023). Power Budgeting for a Processor with Multiple Cores. European Patent Office. EP 21197574.3.

PDF Cite Featured News Article

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Projects

Energy Labels for Ecologically Sustainable Digital Services - A Technological, Behavioural, and Legal Perspective (2023 - 2024)
Energy Labels for Ecologically Sustainable Digital Services - A Technological, Behavioural, and Legal Perspective (2023 - 2024)
Towards Zero-Waste Computing - Energy Labels for Digital Services (2021 - 2025)
Towards Zero-Waste Computing - Energy Labels for Digital Services (2021 - 2025)

UvA Team

Students

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Ehsan Aghapour

Ph.D. Student

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Saeedeh Baneshi

Ph.D. Student

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Sudam Wasala

Ph.D. Student

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Yixian Shen

Ph.D. Student

Researchers

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Dolly Sapra

Postdoctoral Researcher

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Simon Polstra

Sceintfic Programmer

Alumni

Erik Leonards

Bachelor Student

Joris op ten Berg

Master Student

Jurre Wolff

Master Student

Leo Schreuders

Master Student

Martijn Besumusca

Bachelor Student

Sobhan Niknam

Postdoctoral Researcher

Teaching

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All Current Past
Energy Efficient Edge Computing

Energy Efficient Edge Computing

UvA MSc Level Course.

Performance Engineering

Performance Engineering

UvA MSc Level Course.

Embedded Systems

Embedded Systems

UvA BSc Level Course.

Graduation Projects

Graduation Projects

UvA BSc and MSc Levels.

Programming Theory

Programming Theory

UvA BSc Level Course.

Embedded Software and System

Embedded Software and System

UvA MSc Level Course.

Embedded Software Design

Embedded Software Design

NUS BSc Level Course.

Design and Architectures of Embedded System

Design and Architectures of Embedded System

KIT MSc Level Course.

Low Power Design

Low Power Design

KIT MSc Level Course.

Low Power Design and Embedded Systems

Low Power Design and Embedded Systems

KIT BSc Level Course.

Software

CoMeT
Interval Thermal Simulator for 3D Processor-Memory Systems
PDF Code Video User Manual
CoMeT
HotSniper
Interval Thermal Simulator for 2D Multi-/Many-Cores
PDF Code User Manual
HotSniper
Pipe-All
High-Throughput CPU-GPU CNN Inference Pipeline
PDF Code
Pipe-All
T-TSP
Transient-Temperature Based Safe Power Budgeting
PDF Code Patent Featured News Article
T-TSP

News

Hosted Dr. Mitra Nasri for an invited talk 'Past, Present, and Future Trends in Real-Time Systems Research'.
Abstract: Real-time systems are pervasive in the automotive, robotics, smart industry, manufacturing, and healthcare domains, where the system’s safety, dependability, or quality of service depends on both functional and temporal correctness, namely, performing the right actions at the right time.
Sep 6, 2023
Joris op ten Berg successfully defended his Master thesis (with Cum Laude) entitled 'QoS-Aware CPU Scheduling on Simulated Multi-Core Hardware'. Congratulations, Joris!
Abstract: 3D-stacking is a new approach to building CPUs that has the potential to increase performance thanks to low memory access latency. However, stacking components on top of each other increases power density, which results in worse thermals.
Aug 28, 2023
Jurre Wolff successfully defended his Master thesis (with Cum Laude) entitled 'QoS-Aware CPU Scheduling on Simulated Multi-Core Hardware'. Congratulations, Jurre!
Abstract: This thesis introduces program-specific performance statistics as a Central Processing Unit (CPU) scheduling parameter within the context of the HotSniper chip architecture simulation toolchain. The parameter allows for a higher level of program-tailored scheduling, as opposed to the ubiquitous metrics such as types of latency and CPU utilization.
Aug 28, 2023
The paper 'Lifetime Estimation for Core-Failure Resilient Multi-Core Processors' was accepted for IEEE MCSoC '23
Abstract: Multi-core processors come with several cores integrated on a single die. They often work incessantly under high thermal stress, leading to severe wear-out. Server-class multicores already come with a mechanism to survive a core failure called Core Failure Resilience (CFR).
Sudam Wasala, Sobhan Niknam, Anuj Pathania, Clemens Grelck, Andy Pimentel
Aug 10, 2023
The demo/tool 'ARM-CO-UP: ARM Co-Operative Utilization of Processors' was accepted for the Embedded Systems Software Competition at the IEEE/ACM Embedded Systems Week 2023.
Abstract: Heterogeneous Multi-Processor System on Chips (HMPSoCs) combines different processors on a single chip. They enable powerful embedded devices, which increasingly perform Machine Learning (ML) inference at the edge. State-of-the-art HMPSoCs can perform on-chip embedded inference using their CPU, GPU, and integrated accelerators.
Ehsan Aghapour, Dolly Sapra, Andy Pimentel, Anuj Pathania
Aug 1, 2023
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News Tags

Award Current Grant Outreach Paper Past Patent Service Student

Contact

  • a.pathania@uva.nl
  • Room L5.41, Lab 42, Amsterdam, 1098XH
  • Next to NS Science Park Train Station
  • Monday to Friday 10:00 to 18:30 [Open Door Policy]