Erik Leonards successfully defended his Bachelor thesis (with Cum Laude) entitled 'Processor Modelling Using Queueing Theory'. Congratulations, Erik!

Abstract: This thesis gives a general introduction into closed queueing networks, describes mean value analysis and formulates a closed queueing network model that predicts the parallel execution time of multiple benchmarks when the isolated execution time is known. The model aims at imitating the main source of interference between the benchmarks: the DRAM. For an n-core processor, the model comprises n + 1 queues: n cores and the DRAM.

The isolated execution of a benchmark is used to determine the model parameters. The model parameters are chosen such that the measured DRAM throughput and access latency correspond to the DRAM throughput and access latency of the model. The real DRAM throughput and access latency of a benchmark are obtained with the simulation software CoMeT [7], while the DRAM throughput and access latency from the model are obtained from mean value analysis [6].

The accuracy of the model is determined by comparing the parallel benchmark execution time of the model to the real parallel benchmark execution time. This is done for 6 benchmarks in the PARSEC [3] benchmarks suite. For 2 of the benchmarks, the model could very accurately predict the parallel execution time, while the model was less accurate for the other 4 benchmarks.

Anuj Pathania
Anuj Pathania
Assistant Professor

Anuj Pathania is an Assistant Professor in the Parallel Computing Systems (PCS) group at the University of Amsterdam (UvA). His research focuses on the design of sustainable systems deployed in power-, thermal-, energy- and reliability-constrained environments.