Joris op ten Berg successfully defended his Master thesis (with Cum Laude) entitled 'QoS-Aware CPU Scheduling on Simulated Multi-Core Hardware'. Congratulations, Joris!
Abstract: 3D-stacking is a new approach to building CPUs that has the potential to increase performance thanks to low memory access latency. However, stacking components on top of each other increases power density, which results in worse thermals. Higher temperatures in turn cause chips to degrade faster and become less reliable. Schedulers that make decisions to preserve reliability are one of the ways to deal with this challenge. Existing solutions tend to rely on design-time decisions or only use temperature data. We have extended CoMeT, a simulation toolchain capable of simulating 3D-stacked chips, such that it can be used to develop reliability-aware schedulers. To achieve this, we implemented a reliability model that takes temperature and supply voltage into account, and produces a metric of reliability over time. We found that this metric can be used to make scheduling decisions that are aware of a core’s history. Furthermore, we found that using data from the components inside a core could make for more accurate schedulers than when data is collected on the core as a whole.