Jurre Wolff successfully defended his Master thesis (with Cum Laude) entitled 'QoS-Aware CPU Scheduling on Simulated Multi-Core Hardware'. Congratulations, Jurre!

Abstract: This thesis introduces program-specific performance statistics as a Central Processing Unit (CPU) scheduling parameter within the context of the HotSniper chip architecture simulation toolchain. The parameter allows for a higher level of program-tailored scheduling, as opposed to the ubiquitous metrics such as types of latency and CPU utilization. The chip architecture simulator context allows for the development of novel scheduling policies for hard-to-obtain or future CPU architectures. The implementation of the parameter is guided through the first research question concerning how the HotSniper toolchain can be expanded with the Heartbeat framework, which in turn allows for the measurement of program performance. With this question answered, the performance data of eight PARSEC benchmark suite programs is collected and analyzed in pursuit to answer the second research question. This question aims to identify the natural heartbeat profiles and their relation to performance for each of these programs. The third research question then aims to answer whether program performance data can increase task scheduling effectiveness over existing metrics. To help answer these research questions, the HotSniper toolchain is used as a foundation in the form of a practical case study. HotSniper is expanded with functionality allowing for the collection of performance data which is visualized into graphs, revealing program performance profiles.

The collected data of the x264 program resulted in the implementation of a new Quality of Service (QoS) aware Dynamic Voltage and Frequency Scaling (DVFS) policy. It is found that the programspecific performance data allows for setting and achieving QoS targets. For x264, a target of 30 Frames per Second (FPS) is achieved resulting in reduced frequency and power consumption. Based on the results, this study provides five contributions to the computer architecture simulation- and scheduling algorithm research communities. First, a set of eight PARSEC benchmark programs, amended with the Heartbeat framework are provided, along with documentation on how programs in general can be supported. Second, the performance profiles of these programs are collected and analyzed, providing a greater understanding of their runtime behavior and potentially inspiring future research. Third, tooling that supports researchers with post-simulation heartbeat data analysis. Fourth, the HotSniper scheduling Application Programming Interface (API) is updated, allowing for real-time use of performance data and thus the development of performance-aware scheduling policies. Fifth, several identified research directions for future work.

Anuj Pathania
Anuj Pathania
Assistant Professor

Anuj Pathania is an Assistant Professor in the Parallel Computing Systems (PCS) group at the University of Amsterdam (UvA). His research focuses on the design of sustainable systems deployed in power-, thermal-, energy- and reliability-constrained environments.