Scalable Optimal Greedy Scheduler for Asymmetric Multi-/Many-Core Processors

Abstract

Ubiquitous asymmetric multi-core processors such as ARM big.LITTLE combine together cores with different power-performance characteristics on a single chip. Upcoming asymmetric many-core processors are expected to combine hundreds of cores belonging to different types. However, the accompanying task-to-core mapping schedules are the key to achieving the full potential of such processors. Run-time scheduling on asymmetric processors is a much harder problem to solve optimally than scheduling on symmetric processors with equivalent cores. We present the first-ever greedy scheduler to be proven theoretically optimal (under certain constraints) for asymmetric processors. The proposed scheduler, called A-Greedy, improves throughput by 26% and reduces average response time by up to 45% when compared to the default Linux scheduler on ARM big.LITTLE asymmetric multi-core.

Publication
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
Anuj Pathania
Anuj Pathania
Assistant Professor

Anuj Pathania is an Assistant Professor in the Parallel Computing Systems (PCS) group at the University of Amsterdam (UvA). His research focuses on the design of sustainable systems deployed in power-, thermal-, energy- and reliability-constrained environments.