Posts

Abstract: Real-time systems are pervasive in the automotive, robotics, smart industry, manufacturing, and healthcare domains, where the system’s safety, dependability, or quality of service depends on both functional and temporal correctness, namely, performing the right actions at the right time.

Abstract: 3D-stacking is a new approach to building CPUs that has the potential to increase performance thanks to low memory access latency. However, stacking components on top of each other increases power density, which results in worse thermals.

Abstract: This thesis introduces program-specific performance statistics as a Central Processing Unit (CPU) scheduling parameter within the context of the HotSniper chip architecture simulation toolchain. The parameter allows for a higher level of program-tailored scheduling, as opposed to the ubiquitous metrics such as types of latency and CPU utilization.

Abstract: Multi-core processors come with several cores integrated on a single die. They often work incessantly under high thermal stress, leading to severe wear-out. Server-class multicores already come with a mechanism to survive a core failure called Core Failure Resilience (CFR).

Abstract: Heterogeneous Multi-Processor System on Chips (HMPSoCs) combines different processors on a single chip. They enable powerful embedded devices, which increasingly perform Machine Learning (ML) inference at the edge. State-of-the-art HMPSoCs can perform on-chip embedded inference using their CPU, GPU, and integrated accelerators.

Abstract: Convolutional Neural Networks (CNNs) are now quintessential kernels within embedded computer vision applications deployed in edge devices. Heterogeneous Multi-Processor Systemon- Chips (HMPSoCs) with Dynamic Voltage and Frequency Scaling (DVFS) capable components (CPUs and GPUs) allow for lowlatency, low-power CNN inference on resource-constrained edge devices when employed efficiently.

Abstract: This thesis gives a general introduction into closed queueing networks, describes mean value analysis and formulates a closed queueing network model that predicts the parallel execution time of multiple benchmarks when the isolated execution time is known.

Abstract: Convolutional Neural Networks (CNNs) are now quintessential kernels within embedded computer vision applications deployed in edge devices. Heterogeneous Multi-Processor Systemon- Chips (HMPSoCs) with Dynamic Voltage and Frequency Scaling (DVFS) capable components (CPUs and GPUs) allow for lowlatency, low-power CNN inference on resource-constrained edge devices when employed efficiently.