binary calculations and Multy cycle instructions
The objectives for this experiment is to research the operation of the ALU (Arithmetic Logic Unit) and the internals of the multi cycle architecture.
For this experiment use the Lab 2 single cycle architecture and the component 64 bit Multiplier.
Math – by hand method
- Workout a binary (!) multiplication of 0x59 and 0x14. Give the complete multiplication, not just the answer.
- Workout the following binary division: 35 (base 10) / 8 (base 10). Show all steps of the binary division. Use a binary point notation.
- Workout a single precision IEEE notation for the division result. Do the same for a double precision.
Multiplication – Software solution
Load the SingleCycle architecture from Lab2 in the SIM-PL executer.
- Write a short assembly program which multiplies two integers using the MULT instruction.
- How can you retrieve the result?
- Look up the statements for this.
- Write a program which implements figure 3.5 of Patterson and Hennessy.
- Submit the source code as Lab3<YourName>.wasm .
- Compare the CPI of both programs
Math – Hardware solution
Use the multiplier component. Open this component in the executer (use File-> New to open). In the Program Editor window open the file Multiplier.sal. Click on the compile button and download it in the multiplier by clicking on the Red arrow button.
Research the component by changing multiplicand and multiplier. Note that he values have a different base. (Hexadecimal, binary)
- What can you say about the CPI on one multiply instruction?
- if the SingleCycle architecture of lab 2 would be extended with this hardware multiplier as a block near the ALU what will it mean for control lines and data lines?
- What is the effect on the Cycle time of the architecture extension?
- Lookup the opcode/func fields for the MULT instruction. Describe how to produce a control bit to select the multiplier.
- The ALU and multiplier share the same data path to the register file. Describe how you would solve this.
Use the SIM-PL editor for the following experiment. Components needed for the additional circuit are available in the Basic Gates components (Download available from the course webpage.
Implement the hardware multiplier in the lab 2 SingleCycle architecture.
Use the ready bit output signal of the counter unit to stop the multiply execution after 32 steps.
(Hint: add just a little extra hardware) test your solution in the Executer. Submit the architecture and describe the changes in your answer sheet.